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preliminary rev. 0.5 2/08 copyright ? 2008 by silicon laboratories si5322 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5322 p in -p rogrammable p recision c lock m ultiplier description the si5322 is a low jitter, pr ecision clock multiplier for high-speed communication systems, including sonet oc-48/oc-192, ethernet, and fibre channel. the si5322 accepts dual clock inputs ranging from 19.44 to 707 mhz and generates two equal frequency- multiplied clock outputs ranging from 19.44 to 1050 mhz. the input clock frequency and clock multiplication ratio are selectable from a table of popular sonet, ethernet, and fibre channel rates. the si5322 is based on silicon laboratories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operating from a single 1.8, 2.5, or 3.3 v supply, the si5322 is ideal for providing clock multiplication in high performance timing applications. applications ? sonet/sdh oc-48/stm-16 and oc-192/stm-64 line cards ? gbe/10gbe, 1/2/4/8/10gfc line cards ? itu g.709 line cards ? optical modules ? test and measurement features ? selectable output frequencies ranging from 19.44 to 1050 mhz ? low jitter clock outputs with jitter generation as low as 0.6 ps rms (50khz?80mhz) ? integrated loop filter with selectable loop bandwidth (30 khz to 1.3 mhz) ? dual clock inputs with manual or automatically controlled switching ? dual clock outputs with selectable signal format: lvpecl, lvds, cml, cmos ? support for itu g.709 fec ratios (255/238, 255/237, 255/236) ? los alarm output ? pin-controlled output phase adjust ? pin-programmable settings ? on-chip voltage regulator for 1.8 v 5%, 2.5 or 3.3 v 10% operation ? small size: 6 x 6 mm 36-lead qfn ? pb-free, rohs compliant p reliminary d ata s heet dspll ? loss of signal clock select bandwidth select frequency select disable/bypass signal format ckout2 ckin1 ckout1 ckin2 control manual/auto switch signal detect vdd (1.8, 2.5, or 3.3 v) gnd
si5322 2 preliminary rev. 0.5 table 1. performance specifications 1 (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current i dd f out = 622.08 mhz both ckouts enabled lvpecl format output ? 251 279 ma ckout2 disabled ? 217 243 ma f out = 19.44 mhz both ckouts enabled cmos format output ? 204 234 ma ckout2 disabled ? 194 220 ma tristate/sleep mode ? 165 tbd ma input clock frequency (ckin1, ckin2) ck f input frequency and clock multipli- cation ratio pin-selectable from table of values using frqsel and frqtbl settings. consult silicon laboratories configuration software dspll sim or any-rate precision clock family reference manual at www.silabs.com/timing (click on docu- mentation) for table selections. 19.44 ? 707.35 mhz output clock frequency (ckout1, ckout2) ck of 19.44 ? 1049.76 mhz 3-level input pins input mid current i imm see note 2. ?2 ? 2 a input clocks (ckin1, ckin2) differential voltage swing ckn dpp 0.25 ? 1.9 v pp common mode voltage ckn vcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ckn trf 20?80% ? ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns output clocks (ckout1, ckout2) common mode v ocm lvpecl 100 load line-to-line v dd ?1.42 ? v dd ?1.25 v differentia l output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v rise/fall time cko trf 20?80% ? 230 350 ps notes: 1. for a more comprehensive listing of device specifications, pl ease consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3 level input can to lerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5322 preliminary rev. 0.5 3 duty cycle uncertainty cko dc lvpecl differential 100 line-to-line measured at 50% point ?40 ? 40 ps pll performance jitter generation j gen fo = 622.08 mhz, lvpecl output format 50 khz?80 mhz ? 0.6 tbd ps rms 12 khz?20 mhz ? 0.6 tbd ps rms jitter transfer j pk ?0.050.1 db phase noise cko pn f out = 622.08 mhz 100 hz offset ?tbdtbddbc/hz 1 khz offset ? tbd tbd dbc/hz 10 khz offset ? tbd tbd dbc/hz 100 khz offset ? tbd tbd dbc/hz 1 mhz offset ? tbd tbd dbc/hz subharmonic noise sp subh phase noise @ 100 khz offset ? tbd tbd dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ?tbdtbddbc package thermal resistance junction to ambient ja still air ? 38 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.6 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v operating junction temperature t jct ?55 to 150 oc storage temperature range t stg ?55 to 150 oc esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2 kv esd mm tolerance; all pins except ckin+/ckin? 200 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 700 v esd mm tolerance; ckin+/ckin? 150 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications 1 (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit notes: 1. for a more comprehensive listing of device specifications, pl ease consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3 level input can to lerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5322 4 preliminary rev. 0.5 figure 1. typical phase noise plot jitter bandwidth rms jitter (fs) oc-48, 12 khz to 20 mhz 374 oc-192, 20 khz to 80 mhz 388 oc-192, 4 mhz to 80 mhz 181 oc-192, 50 khz to 80 mhz 377 broadband, 800 hz to 80 mhz 420 622 mhz in, 622 mhz out bw=877 khz -170 -150 -130 -110 -90 -70 -50 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz)
si5322 preliminary rev. 0.5 5 figure 2. si5322 typical application circuit si5322 cs_ca 3 c1b c2b frqsel[3:0] 2 bwsel[1:0] 2 sfout[1:0] 2 dbl2_by 2 rst ckout1+ ckout1? vdd gnd input clock select/ active clock indicator frequency select bandwidth select signal format select clock output 2 disable/ bypass mode control reset ckin_1 loss of signal ckin_2 loss of signal clock outputs frqtbl 2 frequency table select ckout2+ ckout2? autosel 2 manual/automatic clock selection (l) 2. denotes tri-level input pins with states designated as l (ground), m (v dd /2), and h (v dd ). ckin1+ ckin1? input clock sources 1 ckin2+ ckin2? notes: 3. assumes manual input clock selection. 1. assumes differential lvepecl termination (3.3 v) on clock inputs. ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 0.1 f 100 0.1 f + ? 0.1 f 100 0.1 f + ? 130 130 82 82 v dd = 3.3 v 130 130 82 82 v dd = 3.3 v v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k
si5322 6 preliminary rev. 0.5 1. functional description the si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including sonet oc-48/oc-192, sdh stm-16/64 ethernet, and fibre channel. the si5322 accepts dual clock inputs ranging from 19.44 to 707 mhz and generates two frequency- multiplied clock outputs ranging from 19.44 to 1050 mhz. the two input clocks are at the same frequency and the two output clocks are at the same frequency. the input clock frequency and clock multiplication ratio are selectable from a table of popular sonet, ethernet, and fibre channel rates. in addition to providing clock multiplication in sonet and datacom applications, the si5322 supports sonet-to-datacom frequency translations. silicon laboratories offers a pc-based software utility, dspll sim , that can be used to look up valid si5322 frequen cy translations. this utility can be downloaded from http://www.silabs.com/timing (click on documentation). the si5322 is recommended for applications in which the input clock is relative ly low jitter and only clock multiplication is required . the si5322 is based on silicon laboratories' 3rd-generation dspll ? technology, which provides any-rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5322 pll loop bandwidth is selectable via the bwsel[1:0] pins and supports a range from 30 khz to 1.5 mhz. the dspll sim software utility can be used to calcul ate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. the si53 22 monitors all input clocks for loss of signal and provides a los alarm when it detects a missing clock. in the case when the input clocks enter alarm conditions, the pll will freeze the dco output frequency near its last val ue to maintain operation with an internal state close to the last valid operating state. the si5322 has two differential clock outputs. the electrical format of the clock outputs is programmable to support lvpecl, lvds, cml, or cmos loads. if not required, the second clock output can be powered down to minimize power consumption. for system-level debugging, a bypass mode is available which drives the output clock directly from th e input clock, bypassing the internal dspll. the device is powered by a single 1.8, 2.5, or 3.3 v supply. 1.1. further documentation consult the silicon laborato ries any-rate precision clock family reference ma nual (frm) for detailed information about the si5322. additional design support is available from silicon laboratories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing ; click on documentation.
si5322 preliminary rev. 0.5 7 2. pin descriptions: si5322 pin assignments are preliminary and subject to change. table 3. si5322 pin descriptions pin # pin name i/o signal level description 1rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logic to a known state. clock out- puts are tristated during reset. after rising edge of rst sig- nal, the si5322 will perform an internal self -calibration. this pin has a weak pull-up. 2 frqtbl i 3-level frequency table select. selects sonet/sdh, datacom, or sonet/sdh to datacom frequency table. l = sonet/sdh. m=datacom. h = sonet/sdh to datacom. the pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an ac tive device that will tri-state. 3c1bolvcmos ckin1 loss of signal. active high loss-of-signal indi cator for ckin1. once trig- gered, the alarm will remain ac tive until ckin1 is validated. 0 = ckin1 present. 1 = los on ckin1. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 frqtbl autosel rst c2b c1b gnd vdd gnd vdd vdd ckin2+ ckin2? dbl2_by vdd ckin1+ ckin1? cs_ca bwsel0 bwsel1 frqsel1 frqsel2 frqsel3 ckout1? sfout1 gnd vdd sfout0 ckout2? ckout2+ nc gnd pad frqsel0 gnd 9 18 19 28 nc nc gnd ckout1+
si5322 8 preliminary rev. 0.5 4c2bolvcmos ckin2 loss of signal. active high loss-of-signal indi cator for ckin2. once trig- gered, the alarm will remain ac tive until ckin2 is validated. 0 = ckin2 present. 1 = los on ckin2. 5, 10, 11, 15, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be associated with the following v dd pins: 5 0.1 f 10 0.1 f 32 0.1 f a 1.0 f should be placed as close to device as is practical. 6, 8,19, 20, 31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. 9 autosel i 3-level manual/automatic clock selection. three level input that selects the method of input clock selection to be used. l = manual. m = automatic non-revertive. h = automatic revertive. the pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an ac tive device that will tri-state. 12 13 ckin2+ ckin2? imulti clock input 2. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from a table of values. the same frequency must be applied to ckin1 and ckin2. 14 dbl2_by i 3-level output 2 disable/bypass mode control. controls enable of ckout2 di vider/output buffer path and pll bypass mode. l = ckout2 enabled. m = ckout2 disabled. h = bypass mode with ckout2 enabled. the pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an ac tive device that will tri-state. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from a table of values. the same frequency must be applied to ckin1 and ckin2. table 3. si5322 pin descriptions (continued) pin # pin name i/o signal level description
si5322 preliminary rev. 0.5 9 21 cs_ca i/o lvcmos input clock select/act ive clock indicator. input : if manual clock selection mode is chosen (autosel = l), this pin functions as the manual input clock selector. this input is internally deglitched to prevent inadvertent clock switching during changes in the cs input state. 0 = select ckin1. 1 = select ckin2. if configured as input, must be set high or low. output : if automatic clock sele ction mode is chosen (autosel = m or h), this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both ckin1 and ckin2, indicating that the digital hold stat e has been entered, ca will indicate the last active cl ock that was used before entering the hold state. 0 = ckin1 active input clock. 1 = ckin2 active input clock. 23 22 bwsel1 bwsel0 i 3-level bandwidth select. three level inputs that select the dspll closed loop band- width. detailed operations and timing characteristics for these pins may be found in the any-rate precision clock family reference manual. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an ac tive device that will tri-state. 27 26 25 24 frqsel3 frqsel2 frqsel1 frqsel0 i 3-level multiplier select. three level inputs that select the input clock and clock multi- plication ratio, depending on the frqtbl setting. consult the any-rate precision clock family reference manual or dspll sim configuration software for settings, both avail- able for download at www.silabs.com/timing (click on docu- mentation). these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an ac tive device that will tri-state. table 3. si5322 pin descriptions (continued) pin # pin name i/o signal level description
si5322 10 preliminary rev. 0.5 33 30 sfout0 sfout1 i 3-level signal format select. three level inputs that select the output signal format (com- mon mode voltage and differential swing) for both ckout1 and ckout2. valid settings include lvpecl, lvds, and cml. also includes selectio ns for cmos mode, tristate mode, and tristate/sleep mode. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an ac tive device that will tri-state. 34 35 ckout2? ckout2+ omulti clock output 2. differential output clock with a frequency selected from a table of values. output signal format is selected by sfout pins. output is differential for lvpecl, lvds, and cml compatible modes. for cmos fo rmat, both output pins drive identical single-ended clock outputs. 29 28 ckout1? ckout1+ omulti clock output 1. differential output clock with a frequency selected from a table of values. output signal format is selected by sfout pins. output is differential for lvpecl, lvds, and cml compatible modes. for cmos fo rmat, both output pins drive identical single-ended clock outputs. 7, 18, 36 nc ? ? no connect. these pins must be left unconnected for normal operation. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5322 pin descriptions (continued) pin # pin name i/o signal level description sfout[1:0] signal format hh reserved hm lvds hl cml mh lvpecl mm reserved ml lvds?low swing lh cmos lm disabled ll reserved
si5322 preliminary rev. 0.5 11 3. ordering guide ordering part number package r ohs6, pb-free temperature range si5322-c-gm 36-lead 6 x 6 mm qfn yes ?40 to 85 c
si5322 12 preliminary rev. 0.5 4. package outline: 36-pin qfn figure 3 illustrates the package details for the si5322. table 4 lis ts the values for the di mensions shown in the illustration. figure 3. 36-pin quad flat no-lead (qfn) table 4. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specif ication for small body components.
si5322 preliminary rev. 0.5 13 5. recommended pcb layout figure 4. pcb land pattern diagram
si5322 14 preliminary rev. 0.5 table 5. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5322 preliminary rev. 0.5 15 d ocument c hange l ist revision 0.44 to revision 0.45 ? condensed format. revision 0.45 to revision 0.46 ? removed references to latency control, inc, and dec in figures and text. ? changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 3. ? added figure 1, ?typical phase noise plot,? on page 4. ? updated ?2. pin descriptions: si5322?. ? added ?5. recommended pcb layout?. revision 0.46 to revision 0.47 ? removed figure 1. ?typ ical phase noise plot.? ? changed pins 11 and 15 from nc to vdd in ?2. pin descriptions: si5322?. revision 0.47 to revision 0.5 ? changed 1.8 v operating range to 5%. ? updated table 1 on page 2. ? updated table 2 on page 3. ? updated figure 2 on page 5 to add pull-up/pull-down resistors for 3-level inputs. ? added figure and table on page 4. ? updated 1."functional description" on page 6. ? clarified 2."pin descriptions: si5322" on page 7. ? updated sfout values.
si5322 16 preliminary rev. 0.5 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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